FeaturesΒΆ

  • Draw and edit timing diagrams with GUI and Python scripts.
  • Add pulses with one mouse click.
  • Add clock synchronous pulses in any signal or bus with one mouse click.
  • Add automatically incrementing and decrementing pulses.
  • Add edge margin color and hash style
  • Timing diagrams automatically created when opening VCD files.
  • Undo and redo
  • Timing analysis with min-max delay margins.
  • User defined part delays and constraints.
  • Select transactions and move complete cycles synchronously
  • Mouse moves edges and text.
  • StateBars to view clock cycles in diagram.
  • Text labels to make notes in diagram.
  • Period labels to show clock periods and pulse widths.
  • TimeWarps compress timing diagram in time.
  • Logic simulation. DFF, Binary Counters, Inverter, Buffer, Differential Driver (More functions coming)
  • Timing diagrams .tim files are text formatted files for easy user control.
  • Image preview showing diagram within common page sizes.
  • Recent file history to quickly load any of last 20 files
  • Automatically loads timing diagrams left open from last session
  • Save diagrams as JPG, GIF, PNG image files, and PS, PDF, and SVG formats.
  • User control of color settings, fonts, font sizes, and more
  • User scripts create custom features.
  • User scripts generate test vectors and testbench files.
  • User scripts quickly draw complex timing diagrams.
  • App note. Generate timing diagrams directly from VHDL simulations.
  • App note. Generate timing diagrams directly from Verilog simulations.
  • App note. Introduction to Timing Analysis
  • Cross platform. Will run on any system with Java Virtual Machine JRE1.6.0 or newer.