Clock based components have constraints that must be met in order to guarantee proper operation. A simple D Flip Flop requires the input data stable for a period in time before the rising clock edge called the setup time (tsetup) and the same input data must also be stable for period in time after the rising clock edge called the hold time(thold). The Q output will change to the new state after a CLK-to-Q propagation delay(tclk2q). The component samples the D input state when CLK rises, and it needs to be stable for the required setup and hold constraint times.
Notice the tsetup time label is orange in the timing diagram. This indicates a constraint error. The tsetup part constraint was added to the timing diagram in line 14. The constraint fails because it requires 6ns minimum, as shown in (1). The thold part constraint was added to the timing diagram in line 15, and the D flip-flop was added in line 17.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
if "new.tim" != taApp.getFileName(): taApp.fileNew("TimingDiagram") td = taApp.getTimingDiagram() td.startScript() clk = td.add_digital_clock("CLK", "H", 20.0e6) d1 = td.add_digital_signal("D", "L") d_e1 = d1.add_edge(95, "H") d_e2 = d1.add_edge(105, "L") clk2q = td.add_part_delay("tclk2q", 6, 6, 8, "DFF Clock to Q Output Delay") setup = td.add_part_constraint("tsetup", 6, 6, "DFF Setup Constraint") hold = td.add_part_constraint("thold", 2, 2, "DFF Hold Constraint") q1 = add_dff_re(td, d1, clk, 'Q', setup, hold, clk2q) td.stopScript()
The output Q would normally go high after tclk2q, the part delay that was added in line 13. But in this case since, the output is not guaranteed to work as expected because of the setup time violation. This delay was specified as 6ns minimum and 8ns maximum. The Grey colored area shows this margin between the min and max edge times.
The D Flip Flop manufacturer specifies the setup and hold constraints, and CLK2Q delay. They are usually shown in the AC characteristics section of the specification.